Synopsys For Physical Design Of Asic Computer Science Essay

Synopsys For Physical Design Of Asic Computer Science Essay IC Compiler is the software package from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the very deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist which can be from DC Compiler or third-party tools, a detailed floorplan which can be from previous Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by manufacturer, and foundry-process data. IC Compiler generates a GDSII-format file as output ready for tape out of the chip. In addition, it is possible to export a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway database, which can be used by other Synopsys tools based on Milkyway. [16] 4.2 User Interfaces IC Compiler can be used either with Shell interface (icc_shell) or with Graphical user interface (GUI). Shell interface is the command-line interface, which is used for batch mode, scripts, typing commands, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical analysis and physical editing tool. Certain tasks, such as very accurately displaying the design and providing visual analysis tools, can only performed from the GUI. Also tool command language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts. The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent timing closure. Figure 4.1 shows the basic IC Compiler design flow, which is centered around three core commands that perform placement and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute optimization (route_opt). [16] icc1 Figure 4.1 IC Compiler Design Flow [21] For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will provide optimal results. You can use IC Compiler to efficiently perform chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges. To further improve the quality of results for your design you can use additional commands and switches for placement, clock tree synthesis, and routing steps that IC Compiler provides. IC Compiler design flow involves execution of following steps: 1. Set up and prepare the libraries and the design data. 2. Perform design planning and power planning. -Design planning is to perform necessary steps to create a floorplan, determine the size of the design, create the boundary and core area, create site rows for the placement of standard cells, set up the I/O pads. -Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current. 3. Perform placement and optimization. IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations. To perform placement and optimization, use the place_opt core command (or from GUI choose Placement menu and then Core Placement and Optimization sub-menu). 4. Perform clock tree synthesis and optimization. To perform the clock tree synthesis and optimization phase, use the command clock_opt (or choose Clock > Core Clock Tree Synthesis and Optimization in the GUI). IC Compiler clock tree synthesis and embedded optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree optimization improves both clock skew and clock insertion delay by performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays. 5. Perform routing and postroute optimization. To perform routing and postroute optimization, use the route_opt core command (or choose Route > Core Routing and Optimization in the GUI). As part of routing and postroute optimization, IC Compiler performs global routing, track assignment, detail routing, search and repair, topological optimization, and engineering change order (ECO) routing. For most designs, the default routing and postroute optimization setup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing the routing and postroute optimization functions for special needs. 6. Perform chip finishing and design for manufacturing tasks. IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the various stages of the design flow to address process design issues encountered during chip manufacturing. 7. Save the design. Save your design in the Milkyway format. This format is the internal database format used by IC Compiler to store all the logical and physical information about a design. [16] 4.3 How to Invoke the IC Compiler 1. Log in to the UNIX environment with the user id and password . 2. Start IC Compiler from the UNIX promt: UNIX$ icc_shell The xterm unix prompt turns into the IC Compiler shell command prompt. 3. Start the GUI. icc_shell> start_gui This window can display schematics and logical browsers, among other things, once a design is loaded. 4.4 Preparing the Design IC Compiler uses a Milkyway design library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format. These steps are explained in the following sections: à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Libraries à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Power and Ground Nets à ¢Ã¢â€š ¬Ã‚ ¢ Reading the Design à ¢Ã¢â€š ¬Ã‚ ¢ Annotating the Physical Data à ¢Ã¢â€š ¬Ã‚ ¢ Preparing for Timing Analysis and RC Calculation à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Design 4.4.1 Setting Up the Libraries IC Compiler requires both logic libraries and physical libraries. The following sections describe how to set up and validate these libraries. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Logic Libraries: IC Compiler uses logic libraries to provide timing and functionality information for all standard cells. In addition, logic libraries can provide timing information for hard macros, such as RAMs. IC Compiler uses variables to define the logic library settings. In each session, you must define the values for the following variables (either interactively, in the .synopsys_dc.setup file, or by restoring the values saved in the Milkyway design library) so that IC Compiler can access the libraries: à ¢Ã¢â€š ¬Ã‚ ¢ search_path Lists the paths where IC Compiler can locate the logic libraries. à ¢Ã¢â€š ¬Ã‚ ¢ target_library Lists the logic libraries that IC Compiler can use to perform physical optimization. à ¢Ã¢â€š ¬Ã‚ ¢ link_library Lists the logic libraries that IC Compiler can search to resolve references. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Physical Libraries: IC Compiler uses Milkyway reference libraries and technology (.tf) files to provide physical library information. The Milkyway reference libraries contain physical information about the standard cells and macro cells in your technology library. In addition, these reference libraries define the placement unit tile. The technology files provide information such as the names and characteristics (physical and electrical) for each metal layer, which are technology-specific. The physical library information is stored in the Milkyway design library. For each cell, the Milkyway design library contains several views of the cell, which are used for different physical design tasks. If you have not already created a Milkyway library for your design (by using another tool that uses Milkyway), you need to create one by using the IC Compiler tool. If you already have a Milkyway design library, you must open it before working on your design. This section describes how to perform the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Create a Milkyway design library To create a Milkyway design library, use the create_mw_lib command (or choose File > Create Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Open a Milkyway design library To open an existing Milkyway design library, use the open_mw_lib command (or choose File > Open Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Report on a Milkyway design library To report on the reference libraries attached to the design library, use the -mw_reference_library option. icc_shell>report_mw_lib-mw_reference_library design_library_name To report on the units used in the design library, use the report_units command. icc_shell> report_units à ¢Ã¢â€š ¬Ã‚ ¢ Change the physical library information To change the technology file, use the set_mw_technology_file command (or choose File > Set Technology File in the GUI) to specify the new technology file name and the name of the design library. à ¢Ã¢â€š ¬Ã‚ ¢ Save the physical library information To save the technology or reference control information in a file for later use, use the write_mw_lib_files command (or choose File > Export > Write Library File in the GUI). In a single invocation of the command, you can output only one type of file. To output both a technology file and a reference control file, you must run the command twice. à ¢Ã¢â€š ¬Ã‚ ¢ Verifying Library Consistency: Consistency between the logic library and the physical library is critical to achieving good results. Before you process your design, ensure that your libraries are consistent by running the check_library command. [16] icc_shell> check_library 4.4.2 Setting Up the Power and Ground Nets IC Compiler uses variables to define names for the power and ground nets. In each session, you must define the values for the following variables (either interactively or in the .synopsys_dc.setup file) so that IC Compiler can identify the power and ground nets: à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic0_net By default, IC Compiler VSS as the ground net name. If you are using a different name, you must specify the name by setting the mw_logic0_net variable. à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic1_net By default, IC Compiler uses VDD as the power net name. If you are using a different name, you must specify the name by setting the mw_logic1_net variable. 4.4.3 Reading the Design IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC files) format. à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in Milkyway Format à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in ASCII Format 4.4.4 Annotating the Physical Data IC Compiler provides several methods of annotating physical data on the design: à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a DEF file To read a DEF file, use the read_def command (or choose File > Import > Read DEF in the GUI). icc_shell> read_def -allow_physical design_name.def à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a floorplan file A floorplan file is a file that you previously created by using the write_floorplan command (or by choosing Floorplan > Write Floorplan in the GUI). icc_shell> read_floorplan floorplan_file_name à ¢Ã¢â€š ¬Ã‚ ¢ Copying the physical data from another design To copy physical data from the layout (CEL) view of one design in the current Milkyway design library to another, use the copy_floorplan command (or choose Floorplan > Copy Floorplan in the GUI). [16] icc_shell> copy_floorplan -from design1 4.4.5 Preparing for Timing Analysis and RC Calculation IC Compiler provides RC calculation technology and timing analysis capabilities for both preroute and postroute data. Before you perform RC calculation and timing analysis, you must complete the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Set up the TLUPlus files You specify these files by using the set_tlu_plus_files command (or by choosing File > Set TLU+ in the GUI). icc_shell> set_tlu_plus_files -tech2itf_map ./path/map_file_name.map -max_tluplus ./path/worst_settings.tlup -min_tluplus ./path/best_settings.tlup à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Back-annotate delay or parasitic data To back-annotate the design with delay information provided in a Standard Delay Format (SDF) file, use the read_sdf command (or choose File > Import > Read SDF in the GUI). To remove annotated data from design, use the remove_annotations command. à ¢Ã¢â€š ¬Ã‚ ¢ Set the timing constraints At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input and output arrival times for each I/O port. This requirement ensures that all signal paths are constrained for timing. To read a timing constraints file, use the read_sdc command (or choose File > Import > Read SDC in the GUI). icc_shell> read_sdc -version 1.7 design_name.sdc à ¢Ã¢â€š ¬Ã‚ ¢ Specify the analysis mode Semiconductor device parameters can vary with conditions such as fabrication process, operating temperature, and power supply voltage. The set_operating_conditions command specifies the operating conditions for analysis. à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Set the derating factors If your timing library does not include minimum and maximum timing data, you can perform simultaneous minimum and maximum timing analysis by specifying derating factors for your timing library. Use the set_timing_derate command to specify the derating factors. à ¢Ã¢â€š ¬Ã‚ ¢ Select the delay calculation algorithm By default, IC Compiler uses Elmore delay calculation for both preroute and postroute delay calculations. For postroute delay calculations, you can choose to use Arnoldi delay calculation either for clock nets only or for all nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory. [16] 4.4.6 Saving the Design To save the design in Milkyway format, use the save_mw_cel command (or choose File > Save Design in the GUI). [16] CHAPTER 5: Design Planning 5.1 Introduction Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan groups, in-place optimization, prototype global routing analysis, hierarchical clock planning, performing pin assignment on soft macros and plan groups, performing timing budgeting, converting the hierarchy, and refining the pin assignment. Power network synthesis and power network analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. Power network analysis validates the power synthesis results by performing voltage-drop and electromigration analysis. [16] Figure 5.1 IC Compiler Design Planning [21] 5.2 Tasks to be performed during Design Planning à ¢Ã¢â€š ¬Ã‚ ¢ Initializing the Floorplan à ¢Ã¢â€š ¬Ã‚ ¢ Automating Die Size Exploration à ¢Ã¢â€š ¬Ã‚ ¢ Handling Black Boxes à ¢Ã¢â€š ¬Ã‚ ¢ Performing an Initial Virtual Flat Placement à ¢Ã¢â€š ¬Ã‚ ¢ Creating and Shaping Plan Groups à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing Prototype Global Routing à ¢Ã¢â€š ¬Ã‚ ¢ Performing Hierarchical Clock Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing In-Place Optimization à ¢Ã¢â€š ¬Ã‚ ¢ Performing Routing-Based Pin Assignment à ¢Ã¢â€š ¬Ã‚ ¢ Performing RC Extraction à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Analysis à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Budgeting à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Physical Hierarchy à ¢Ã¢â€š ¬Ã‚ ¢ Refining the Pin Assignment 5.3 Initializing the Floorplan The steps in initializing the floorplan are described below. à ¢Ã¢â€š ¬Ã‚ ¢ Reading the I/O Constraints: To load the top-level I/O pad and pin constraints, use the read_io_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Defining the Core and Placing the I/O Pads: To define the core and place the I/O pads and pins, use the initialize_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Rectilinear-Shaped Blocks: Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a fixed set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape L|T|U|X. à ¢Ã¢â€š ¬Ã‚ ¢ Writing I/O Constraint Information: To write top-level I/O pad or pin constraints, use the write_io_constraints command. Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Cell Rows: To add cell rows, use the add_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Removing Cell Rows: To remove cell rows, use the cut_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Floorplan Information: To save the floorplan information, use the write_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢Writing Floorplan Physical Constraints for Design Compiler Topographical Technology: IC Compiler can now write out the floorplan physical constraints for Design Compiler Topographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax is: write_physical_constraints -output output_file_name -port_side [16] Figure 5.2 Floor Plan After Initialization [21] 5.4 Automating Die Size Exploration This section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, die size for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage drop requirements. The technology is integrated into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view. 5.5 Handling Black Boxes Black boxes can be represented in the physical design as either soft or hard macros. A black box macro has a fixed height and width. A black box soft macro sized by area and utilization can be shaped to best fit the floorplan. To handle the black boxes run the following set of commands. set_fp_base_gate estimate_fp_black_boxes flatten_fp_black_boxes create_fp_placement place_fp_pins create_qtm_model qtm_bb set_qtm_technology -lib library_name create_qtm_port -type clock $port report_qtm_model write_qtm_model -format qtm_bb report_timing qtm_bb 5.6 Performing an Initial Virtual Flat Placement The initial virtual flat placement is very fast and is optimized for wire length, congestion, and timing. The way to perform an initial virtual flat placement is described below. à ¢Ã¢â€š ¬Ã‚ ¢ Evaluating Initial Hard Macro Placement: No straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on practical design experience. à ¢Ã¢â€š ¬Ã‚ ¢ Specifying Hard Macro Placement Constraints: Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement. Creating a User-Defined Array of Hard Macros Setting Floorplan Placement Constraints On Macro Cells Placing a Macro Cell Relative to an Anchor Object Using a Virtual Flat Placement Strategy Enhancing the Behavior of Virtual Flat Placement With the macros_on_edge Switch Creating Macro Blockages for Hard Macros Padding the Hard Macros à ¢Ã¢â€š ¬Ã‚ ¢ Padding the Hard Macros: To avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined padding distance or keepout margin around the macros. One can set this padding distance on a selected macros cell instance master.During virtual flat placement no other cells will be placed within the specified distance from the macros edges. [16] To set a padding distance (keepout margin) on a selected macros cell instance master, use the set_keepout_margin command. à ¢Ã¢â€š ¬Ã‚ ¢ Placing Hard Macros and Standard Cells: To place the hard macros and standard cells simultaneously, use the create_fp_placement command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Floorplan Editing: IC Compiler performs the following floorplan editing operations. Creating objects Deleting objects Undoing and redoing edit changes Moving objects Changing the way objects snap to a grid Aligning movable objects 5.7 Creating and Shaping Plan Groups This section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific region of the core area. This section also describes how to automatically place and shape objects in a design core, add padding around plan group boundaries, and prevent signal leakage and maintain signal integrity by adding modular block shielding to plan groups and soft macros. The following steps are covered for Creating and Shaping Plan Groups. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Plan Groups: To create a plan group, create_plan_groups command. To remove (delete) plan groups from the current design, use the remove_plan_groups command. à ¢Ã¢â€š ¬Ã‚ ¢ Automatically Placing and Shaping Objects In a Design Core: Plan groups are automatically shaped, sized, and placed inside the core area based on the distribution of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed; the other blocks, whether or not they are inside the core, are subject to being moved or reshaped. To automatically place and shape objects in the design core, shape_fp_blocks command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Padding to Plan Groups: To prevent congestion or DRC violations, one can add padding around plan group boundaries. Plan group padding sets placement blockages on the internal and external edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding. To add padding to plan groups, create_fp_plan_group_padding command. To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Block Shielding to Plan Groups or Soft Macros: When two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the outside of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro. To add block shielding for plan groups or soft macros, use the create_fp_block_shielding command. To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. [16] 5.8 Performing Power Planning After completed the design planning process and have a complete floorplan, one can perform power planning, as explained below. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Logical Power and Ground Connections: To define power and ground connections, use the connect_pg_nets command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Rings: It is necessary to add power and ground rings after doing floorplanning. To add power and ground rings, use the create_rectangular_rings command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Straps: To add power and ground straps, use the create_power_straps command. à ¢Ã¢â€š ¬Ã‚ ¢ Prerouting Standard Cells: To preroute standard cells, use the preroute_standard_cells command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Low-Power Planning for Multithreshold-CMOS Designs: One can perform floorplanning for low-power designs by employing power gating. Power gating has the potential to reduce overall power consumption substantially because it reduces leakage power as well as switching power. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Network Synthesis: As the design process moves toward creating 65-nm transistors, issues related to power and signal integrity, such as power grid generation, voltage (IR) drop, and electromigration, have become more significant and complex. In addition, this complex technology lengthens the turnaround time needed to identify and fix power and signal integrity problems. By performing power network synthesis one can preview an early power plan that reduces the chances of encountering electromigration and voltage drop problems later in the detailed power routing. To perform the PNS, one can run the set of following commands. [16] synthesize_fp_rail set_fp_rail_constraints set_fp_rail_constraints -set_ring set_fp_block_ring_constraints set_fp_power_pad_constraints set_fp_rail_region_constraints set_fp_rail_voltage_area_constraints set_fp_rail_strategy à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Power Plan: Once the IR drop map meets the IR drop constraints, one can run the commit_fp_rail command to transform the IR drop map into a power plan. à ¢Ã¢â€š ¬Ã‚ ¢ Handling TLUPlus Models in Power Network Synthesis: Power network synthesis supports TLUPlus models. set_fp_rail_strategy -use_tluplus true à ¢Ã¢â€š ¬Ã‚ ¢ Checking Power Network Synthesis Integrity: Initially, when power network synthesis first proposes a power mesh structure, it assumes that the power pins of the mesh are connected to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. After the power mesh is committed, one might discover problem areas in design as a result of automatic or manual cell placement. These areas are referred to as chimney areas and pin connect areas. To Check the PNS Integrity one can run the following set of commands. set_fp_rail_strategy -pns_commit_check_file set_fp_rail_strategy -pns_check_chimney_file set_fp_rail_strategy -pns_check_chimney_file pns_chimney_report set_fp_rail_strategy -pns_check_hor_chimney_layers set_fp_rail_strategy -pns_check_chimney_min_dist set_fp_rail_strategy -pns_check_pad_connection file_name set_fp_rail_strategy -pns_report_pad_connection_limit set_fp_rail_strategy -pns_report_min_pin_width set_fp_rail_strategy -pns_check_hard_macro_connection file_name set_fp_rail_strategy -pns_check_hard_macro_connection_limit set_fp_rail_strategy -pns_report_min_pin_width à ¢Ã¢â€š ¬Ã‚ ¢ Analyzing the Power Network: One perform power network analysis to predict IR drop at different floorplan stages on both complete and incomplete power nets in the design. To perform power network analysis, use the analyze_fp_rail command. To add virtual pads, use the create_fp_virtual_pad command. To ignore the hard macro blockages, use the set_fp_power_plan_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Viewing the Analysis Results: When power and rail analysis are complete, one can check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. One can save the results of voltage drop and electromigration current density values to the database by saving the CEL view that has just been analyzed. à ¢Ã¢â€š ¬Ã‚ ¢ Reporting Settings for Power Network Synthesis and Power Network Analysis Strategies: To get a report of the current values of the strategies used by power network synthesis and power network analysis by using the report_fp_rail_strategy command. [16] 5.9 Performing Prototype Global Routing One can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect possible congestion hot spots that might exist in the floorplan due to the placement of the hard macros or inadequate channel spacing. To perform global routing, use the route_fp_proto command. 5.10 Performing Hierarchical Clock Planning This section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Clock Planning Options: To set clock planning options, use the set_fp_clock_plan_options command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Clock Planning Operations: To perform clock planning operations, use the compile_fp_clock_plan command. à ¢Ã¢â€š ¬Ã‚ ¢ Generating Clock Tree Reports: To generate clock tree reports, use the report_clock_tree command. à ¢Ã¢â€š ¬Ã‚ ¢ Using Multivoltage Designs in Clock Planning: Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Plan Group-Aware Clock Tree Synthesis in Clock Planning: With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during partitioning and budgeting. [16] 5.11 Performing In-Place Optimization In-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed: timing improvement, area recovery, and fixing DRC violations. T

Tora: an emblem of New Woman

Ibsen was a powerful Norwegian playwright who left no stone unturned to explore all the critical problems of the society right from his Pillars of the Society ,Ghosts   to The Enemy of People. Ibsen was really disturbed to find that women were being turned into mere gewgaws of the household ,to decorate the house, to nod at every odd proposal put forth by her husband, i.e, the master of the household, to dance to his tune all the time to keep the peace and harmony of home intact. He was such aggrieved to observe this   unhealthy balance ,that he composed the brilliant play A Doll’s House, considered to be one of the best plays that marks a new epoch in the history of women’s emancipation. Ibsen himself wrote â€Å"The wife in the play ends by having no idea of what is right or wrong; natural feeling on the hand and belief in authority on the other have altogether bewildered her. A woman cannot be herself in the society of the present day ,which is an exclusively masculine society ,with laws framed by men and with a judicial system that judges feminine conduct from a masculine point of view.†[Cf. Ibsen, Henrik:Notes for the Modern Tragedy ] Hence, Ibsen was very much aware of the fact that the housekeeping woman-cum-wife was invariably looked down upon by the male chauvinistic husband. Why not look at Nora Helmer and her position in the household from   close   quarters? In the very first act , when she enters with a load of parcels in her hand and interacts with her husband Torvald , she is addressed at least more than once as â€Å"featherbrain†, â€Å"scatterbrain† so forth. It may be so taken for granted that Torvald driven by the unalloyed passion of love for her wife addresses her in like terms. So far as ‘songbird’ , ‘doll-wife’ go that may have some significance. But, when Torvald unhesitatingly utters, â€Å"You wouldn’t believe how much it costs a man when he’s got a little songbird like you†, his dormant chauvinism suddenly pops up to the open. Does he not mean to belittle the labor his wife is incessantly putting in to run the household smoothly , that too, not in expectation of any material gain for herself in turn? Yes, he does, whether   he intends to mean so or not. In Act One itself, it becomes crystal clear to us that Nora loved her husband so deeply that she never hesitated   to forge a document when it came to the decision of saving her husband’s life. She even confessed of working as a copywriter for sometime working late into the night burning her midnight oil and energy.Why? TO SAVE HER HUSBAND†S PRECIOUS LIFE!!And what did she get in turn? Nora’s interaction with Mr. Krogstad too was not out of the necessities of profession. The letter that he left shoving her to the brink of destruction was rectified later on by another letter of contrition. But , the matters had tuned worse by then. Our query to the playwright is ,if Nora got the taste of earning like a man by copywriting why did she not continue with it and accrue some   sort of self-complacency by seeing herself dependent? Perhaps, the subjugation of women in that era for which Mary Wollstonecraft and others of that period fought was stifling her to death from within! Knowingly, unknowingly, or whatever!! Mr. Krogstad at one point started pestering Nora to influence her husband for retaining him as his subordinate in the bank. Thereafter, this sneaking man went to such a daring extent that Nora could not disown him, knowing full well that this man was more venomous than a viper. Mr. Krogstad started blackmailing Nora with such incriminating statements like, â€Å"Your father died on the twenty-ninth of September. But look at this –your father has dated his signature the second of October. Isn’t that a curious thing, Mrs. Helmer?† [Nora is silent] Can you explain it?†[A Doll’s House,Act One] Nora was caught into the snare and lastly when the act of unintentional forgery stood exposed to Torvald in Act Three and he hit the roof ,accusing his doll-wife   with harsh words ,Nora   had every reason to give vent to her pent-up hurt feelings. She felt humiliated when Torvald pointed rude and naked finger to her dead father’s moral failings and detested her for inheriting so. Was it not the most heinous form of accusation? Torvald could demean her , could call her names even, but was it really ethical of him as a son-in-law to bring down the house at the expense of his dead father-in-law’s moral turpitude? That might be utterly baseless even! Even after such humiliation Nora could utter , â€Å"I’ve loved you more than anything in the world.† Torvald cast aspersions on her by calling her â€Å"liar†, â€Å"hypocrite† even worse, â€Å"a criminal†. She had inherited her father’s shiftless character by proving herself   irreligious, immoral, irresponsible! Nora went on listening all the odorous, obnoxious accusations maintaining her cool. And , even when Torvald thundered, â€Å"And I’m brought so pitifully low all because of a shiftless woman!† she remained surprisingly calm rejoining only, â€Å"Once I’m out of the way, you’ll be free.† Torvald went a step further and snowballed his unguarded comment, You will remain here in my house —that goes without saying—but I shall not allow you to bring up my children†¦.I shouldn’t dare trust you with them†, then could any motherly sentiment remain untouched ? Nora’s heart too bled profusely at such ruthless utterance. That was why, it took hardly a few seconds for her to decide to slam the door on her husband’s face at last! When the letter of repentance or redress reached Torvald, he in the same peremptory tone spoke out, â€Å"Nora, I’m saved.†Nora in a passive tone inquired of her position, â€Å"And I?† With intense passion,Torvald said, â€Å"You too of course.† After such mindless , pointless   humiliation , how could Torvald be so inane to belt out the words, â€Å"I’ve forgiven you..†?† We are surprised to see Nora turning back to look stern at him , thus intimidating him. Nora pulled up all her courage to blurt out on his face, â€Å"You’ve never loved me, you’ve only found it   pleasant to be in love with me.†Therafter , Nora went on expatiating her restrained attitude in both her father’s house and later at her husband’s . She admitted of dancing to both her father’s and husband’s tunes , as the cases might have been. Later on with much conviction the revelation dawned upon her, â€Å"You and Papa have committed a grievous sin against me: it’s your fault that I’ve made nothing of my life.† She never had the courage to express her own opinion. Now she mustered her guts to speak out and think independently with her own grey cells!! Now she was not hesitant to say that she was never happy at Torvald’s , but only â€Å"gay†. Nora felt the need of educating herself, she was keen on standing on her own feet ,if she was to know herself and the world outside. Her tongue did not falter to utter, â€Å"That’s why I can’t stay here with you any longer.†This daring statement could only suffice to bring   a New Woman   out of conventional Nora ,a   doll-wife ,in the era when voicing   a protest against a husband   was simply next to impossible!! Nora lastly hit the bull’s eye by saying that life could hardly be a real marriage for a couple who pretended all he time to be HAPPY!! It was the greatest miracle of all when Nora left the house slamming the door behind. The house appeared EMPTY to Torvald. We were being prepared throughout the play for this final action from Nora. Her unrequited love for her husband , for her family shoved her to the edge of utter denial . The children for whom she spent her last farthing to buy the costliest Christmas gift , too, could not be trusted with her!! Such utterance drove her desperate, insane and her decision seemed appropriate.However inane it might appear at the outset, it brought to the fore a revolutionary   and protesting self   of a woman who hated demeaning her womanhood. As economic freedom happened to be a significant criterion of a free woman , will it be very wrong to say that Nora of Ibsen foreshadowed Lily Briscoe of Virginia Woolf or her thought of an earning woman as a New Woman as appeared in her A Room of one’s Own?As in later days we find Michele Foucault arguing   about self-refusal rather than self-discovery,by which he meant to say that ‘to become what she was not at the beginning.† Thus, the concept of New Woman which was taking shape with Mother Courage of Brecht or Wife of Bath of Chaucer even much earlier found a veritable shape in Nora Helmer. Nora was truly justified to rise up in arms against the abominable subjugation inflicted on her and Ibsen was assiduously preparing the audience right from Act One for such a finale. Of course, Nora had every right to chime in with a contemporary woman-poet, Anna Laetitia Barbauld, â€Å"Yes,injured Woman!rise, assert thy right! Woman!too long degraded , scorned, oppressed; O born to rule in partial Law’s despite, Resume thy native empire o’er the breast.†[The Rights of Woman] Works Cited 1.Ibsen , Henrik[Tr. Peter Watts]:A Doll’s House and Other Plays, Penguin, England, 1965. 2.Cole, Toby ed: Playwrights on Playwriting,Colonial Press, USA, 1960. 3.Pritchard, R.E.ed:Poetry by English Women ,Elizabethan to Victorian, Continuum, New York, 1990. 4.Meyer, Michael:Ibsen, Penguin, England, 1967. 5, Gatting, Gary ed:The Cambridge Comapanion to Foucault, CUP, New York, 1994.            

Main Theoretical Perspectives Within Sociology - 1330 Words

A theory is a statement that explains how and why the world operates the way it does. Theories are a great part of the framework used in organizing the specific social phenomena’s within social science. Theories can answer questions like why certain groups of people all live in the same/ certain neighborhood. Theories try to explain why groups of people do certain things, and why a society changes and how it works. There are three main theoretical perspectives within sociology. These perspectives are functionalism, symbolic interactionism and, conflict theory. To understand phenomena as to the ways groups are formed it is important to follow theoretical perspectives. A theory is a general statement about how some parts of the world fit together and how they work. It is an explanation of how facts are related to one other. While a fact is an observation that has been proven over and over and has been accepted as being true. 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